Semiconductor wafer, semiconductor device and method of fabricating the same

ABSTRACT

A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2007-218459, filed on Aug. 24,2007, the entire contents of which are incorporated herein by reference.

BACKGROUND

In a structure of a fin-type FET (Field Effect Transistor) (hereinafterreferred to as “FinFET”), it is possible to provide several channelplane directions by setting a crystal plane direction and a channeldirection of a substrate. Furthermore, it is known that an optimalchannel direction with respect to a crystal axis to improve carriermobility is different between an n-type FinFET and a p-type FinFET. Forexample, in general, both of the n-type and p-type FinFETs are oftenconfigured so that a plane direction of a fin side surface is (100) andan axial direction of a channel region formed on the fin side surface is<110>, however, it has been known that the carrier mobility is improvedby configuring the plane direction of the fin side surface to be (100)and the axial direction of the channel region formed on the fin sidesurface to be <100> for the n-type FinFET while configuring the planedirection of the fin side surface to be (110) and the axial direction ofthe channel region formed on the fin side surface to be <110> for thep-type FinFET.

A technique to form one conductivity type of FinFET inclined at 45° withrespect to another conductivity type of FinFET around a height directionso as to make plane directions and channel directions of fin sidesurfaces of both n-type and p-type FinFETs to be directions whichimprove the carrier mobility as described above when mounting the n-typeand p-type FinFETs together on a Si substrate of which plane directionof one principal surface is (100), is known. This technique, forexample, is disclosed in a non-patent literary document of B. Doris etal., Symp. on VLSI Tech. Dig. of Tech. Papers, pp. 86-87, 2004.

Meanwhile, a technique, to give different crystal directions to ann-type and p-type device regions on the same substrate, in whichsemiconductor substrates having different plane directions arelaminated, and then, a predetermined region of the upper substraterecrystallized so as to reflect a plane direction of the lower substrateafter amorphizing the predetermined region of the upper substrate, isknown. This technique, for example, is disclosed in U.S. Pat. No.7,023,055.

BRIEF SUMMARY

A semiconductor substrate according to one embodiment includes: a firstsemiconductor wafer having a first crystal; and a second semiconductorwafer formed of a second crystal substantially same as the first crystalon the first semiconductor wafer, a crystal-axis direction of unit cellthereof being twisted at a predetermined angle around a directionvertical to a principal surface of the second semiconductor wafer fromthat of the first semiconductor wafer.

A semiconductor device according to another embodiment includes: asemiconductor substrate; a first transistor formed on the semiconductorsubstrate and having a first fin; and a second transistor formed on thesemiconductor substrate and having a second fin of which plane directionof the upper surface is identical to that of the first fin, a channeldirection in the second fin with respect to a crystal axis of the sidesurface portion of the second fin being different from a channeldirection in the first fin with respect to a crystal axis of the sidesurface portion of the first fin, and a direction in which the secondfin is arranged being substantially parallel or vertical to a directionin which the first fin is arranged within a plane parallel to a surfaceof the semiconductor substrate.

A method of fabricating a semiconductor device according to anotherembodiment includes: laminating a second substrate, of which planedirection of the principal surface is same as that of a first substrate,on the first substrate in the state that the crystal-axis directions inthe principal surfaces of the first and second substrates are at apredetermined angle around a direction vertical to the principal surfaceto each other, forming first and second fins by patterning the secondsubstrate, selectively amorphizing the first fin; and substantiallymatching the crystal-axis direction of the unit cell of the first fin tothat of the first substrate by recrystallizing the amorphized first finusing the first substrate as a base.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a semiconductor device according to afirst embodiment;

FIG. 2 is a cross sectional view of the semiconductor device accordingto the first embodiment when a cut surface taken on line II-II of FIG. 1is viewed in a direction indicated by an arrow in the figure;

FIG. 3 is a cross sectional view of the semiconductor device accordingto the first embodiment when a cut surface taken on line III-III of FIG.1 is viewed in a direction indicated by an arrow in the figure;

FIGS. 4A to 4K are cross sectional views showing processes forfabricating the semiconductor device according to the first embodiment;

FIG. 5 is a cross sectional view of the semiconductor device accordingto a second embodiment;

FIGS. 6A to 6E are cross sectional views showing processes forfabricating the semiconductor device according to the second embodiment;

FIGS. 7A to 7C are cross sectional views showing processes forfabricating the semiconductor device according to a third embodiment;and

FIG. 8 is a cross sectional view of a semiconductor device according toa fourth embodiment.

DETAILED DESCRIPTION First Embodiment

FIG. 1 is a perspective view of a semiconductor device according to afirst embodiment. Furthermore, FIG. 2 is a cross sectional view when acut surface taken on line II-II of FIG. 1 is viewed in a directionindicated by an arrow in the figure. Furthermore, FIG. 3 is acrosssectional view when a cut surface taken on line III-III of FIG. 1 isviewed in a direction indicated by an arrow in the figure.

A semiconductor device 1 schematically has a n-type FinFET 10 and ap-type FinFET 20 formed on a semiconductor substrate 2 and a deviceisolation region 3 for electrically isolating the n-type FinFET 10 andthe p-type FinFET 20. Note that, instead of the n-type FinFET 10 and thep-type FinFET 20, tri-gate transistors in which a channel region isformed on both side faces and an upper surface of a fin may be used.

The n-type FinFET 10 and the p-type FinFET 20 include fins 11 and 21formed on the semiconductor substrate 2, and gate electrodes 14 and 24formed so as to sandwich both side faces of the fins 11 and 21 betweentheir opposite portions via gate insulating films 12 and 22,respectively. Furthermore, cap films 13 and 23 are formed between thegate electrodes 14 and 24 and the upper surfaces of the fins 11 and 21.In addition, an oxide film 4 is formed between the fin 21 and thesemiconductor substrate 2. Source/drain regions 11 a and 21 a are formedin regions which sandwich the gate electrodes 14 and 24 in the fins 11and 21, respectively and channel regions 11 b and 21 b are formed inregions sandwiched by the source/drain regions 11 a and 21 a in the fins11 and 21. Note that, illustrations of the source/drain regions 11 a and21 a and the channel regions 11 b and 21 b are omitted in FIG. 1 andFIG. 2.

Furthermore, a punch-through stopper may be formed in a region locatedsubstantially below the upper surface of the device isolation region 3in the fins 11 and 21 even though it is not illustrated. Gate sidewallspacers or offset spacers may be formed on the side faces of the gateelectrodes 14 and 24, respectively even though they are not illustrated.

For the semiconductor substrate 2, for example, it is possible to use aSi-based substrate comprising a crystal mainly composed of Si such as aSi substrate or the like, of which plane direction of the principalsurface is {100}. Note that, {100} represents (100) and a planedirection equivalent to (100).

The device isolation region 3 comprises, for example, an insulatingmaterial such as SiO₂ or the like, and has a STI (Shallow TrenchIsolation) structure.

For the fin 11 of the n-type FinFET 10, it is preferable that the planedirection of the side face is {100} and a channel direction 11 c of thechannel region 11 b formed on the side face is <100> for the reason forimproving mobility of an electron which is a carrier. Note that, <100>represents [100] and a direction equivalent to [100]. Furthermore, acrystal-axis direction of the unit cell of a crystal composing the fin11 substantially matches that of a crystal comprising the semiconductorsubstrate 2.

For the fin 21 of the p-type FinFET 20, it is preferable that the planedirection of the side face is {110} and a channel direction 21 c of thechannel region 21 b formed on the side face is <110> for the reason forimproving mobility of a hole which is a carrier. Note that, <110>represents [110] and an axial direction equivalent to [110].Furthermore, a crystal-axis direction of the unit cell of a crystalcomposing the fin 21 and that of a crystal composing the semiconductorsubstrate 2 are mismatched at a predetermined angle θ around a directionvertical to the side face of the semiconductor substrate 2. Thispredetermined angle θ is preferably θ=(45+90×n)° (n is an integernumber).

Furthermore, it is preferable that channel directions 11 c and 21 c inthe fins 11 and 21 are formed substantially parallel or vertical to eachother within a plane parallel to the surface of the semiconductorsubstrate 2 for the convenience of the layout or the like of devices onthe semiconductor substrate 2. Furthermore, it is preferable that thefins 11 and 21 have a sufficient height in order to prevent thesource/drain region 21 a formed inside the fin 21 from being formed to aposition below the oxide film 4. It is because a current path is formedbelow the channel region 21 b which is governed by the gate insulatingfilm 22 and a punch-through is possibly generated if the source/drainregion 21 a is formed to a position below the oxide film 4.

Furthermore, the fins 11 and 21 are composed of a crystal which issubstantially identical to the crystal composing the semiconductorsubstrate 2. Here, “substantially identical” means that those crystalsare identical if parent crystals (Si crystal, etc.) are identical,unless axial angles of the unit cell or the like vary greatly, even ifthe contained amounts of the impurity atom or the like are different.

The gate insulating films 12 and 22 are composed of, for example, SiO₂,SiN, SiON, or a high-k material (for example, an Hf-based material suchas HfSiON, HfSiO or HfO, a Zr-based material such as ZrSiON, ZrSiO orZrO, and a Y-based material such as Y₂O₃).

The cap films 13 and 23 are composed of, for example, an insulatingmaterial such as SiN or the like. Note that, when the n-type FinFET 10and the p-type FinFET 20 are tri-gate transistors, the cap films 13 and23 are not provided, the gate insulating films 12 and 22 are providedalso on the upper surface of the fins 11 and 21, respectively, and thechannel regions 11 b and 21 b are formed also in the upper surface ofthe fins 11 and 21.

The gate electrodes 14 and 24 are composed of, for example,polycrystalline silicon containing a conductivity type impurity orpolycrystalline silicon germanium containing a conductivity typeimpurity. In terms of the conductivity type impurity, a p-type impurityion such as B, BF₂, In or the like is used for a p-type transistor andan n-type impurity ion such as As, P or the like is used for an n-typetransistor. Note that, silicide layers may be formed on the surfaces ofthe gate electrodes 14 and 24. Furthermore, the gate electrodes 14 and24 may be composed of fully silicided gate electrode, of which wholeregion is silicided. Furthermore, the gate electrodes 14 and 24 may be ametal gate electrode composed of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo, Alor the like or a compound thereof, or may have a laminated structure ofa metal gate electrode portion and a polysilicon electrode portion.

An example of the processes for fabricating the semiconductor device 1according to this embodiment will be described hereinafter.

FIGS. 4A to 4K are cross sectional views showing processes forfabricating the semiconductor device according to the first embodiment.Note that, the cross sections shown in these figures correspond to thecross section shown in FIG. 2.

Firstly, as shown in FIG. 4A, a second semiconductor substrate 5 islaminated on the semiconductor substrate 2 and an insulating film 6 isformed thereon. Here, the second semiconductor substrate 5 is composedof a crystal which is substantially identical to the crystal composingthe semiconductor substrate 2, for example, a Si crystal. Furthermore,in the second semiconductor substrate 5, the plane direction of theprincipal surface is identical to that of the semiconductor substrate 2and the crystal-axis direction of the unit cell is at a predeterminedangle θ around a direction vertical to the surface thereof with that ofthe semiconductor substrate 2. Especially, it is preferable that theplane directions of the principal surfaces of the semiconductorsubstrate 2 and the second semiconductor substrate 5 are {100} andθ=(45+90×n)° (n is an integer number).

For laminating the semiconductor substrate 2 and the secondsemiconductor substrate 5, it is possible to use a method to formhydrophilic bonding between the semiconductor substrate 2 and the secondsemiconductor substrate 5 under low temperature or a method to formhydrophobic bonding between the semiconductor substrate 2 and the secondsemiconductor substrate 5 under high temperature. Note that, since it isdifficult to match the crystal lattice neatly in order of atomic sizeeven if the plane directions of the substrates are same, the oxide film4 which is an ultrathin film is often formed partially on the interfacebetween the semiconductor substrate 2 and the second semiconductorsubstrate 5 when laminating the semiconductor substrate 2 and the secondsemiconductor substrate 5. The following explanation describe the casethat the oxide film 4 is formed. However the explanation will be appliedto the case that the oxide film 4 is not formed.

Furthermore, since the heights of the fins 11 and 21 are determined bythe thickness of the second semiconductor substrate 5, the secondsemiconductor substrate 5 is required to have sufficient thickness inorder to prevent the source/drain region formed in the fin 21 from beingformed below the oxide film 4 in the posterior process. On the otherhand, if the thickness of the second semiconductor substrate 5 isexcessive, it becomes difficult to recrystallize the fin 11 using thesemiconductor substrate 2 as a base in the posterior process.Concretely, for example, when the height of the fin 21 from the surfaceof the device isolation region 3 is 100 nm, the thickness of the secondsemiconductor substrate 5 is 200 nm.

Following method is used for adjusting an in-plane angle of thesubstrate when laminating the semiconductor substrate 2 and the secondsemiconductor substrate 5. For example, substrates in which marksindicating directions of the crystal such as notches, orientation flatsor the like are provided in a direction preliminarily located at anangle θ to each other are used as the semiconductor substrate 2 and thesecond semiconductor substrate 5, and are laminated with aligning(matching) the positions of the notches or the like of the semiconductorsubstrate 2 and the second semiconductor substrate 5. Concretely, it ispossible to use a substrate, of which the plane direction of theprincipal surface is {100} and a notch or the like is formed in a <100>direction of the principal surface, as the semiconductor substrate 2 anda substrate, in which the {100} plane direction of the principal surfaceis {100} and a notch or the like is formed in a <110> direction of theprincipal surface, as the second semiconductor substrate 5, and laminatethe semiconductor substrate 2 and the second semiconductor substrate 5with aligning the positions of the notches or the like thereof.

Furthermore, it may use the same substrates, in which the notches or thelike are provided in the same direction, as the semiconductor substrate2 and the second semiconductor substrate 5, and laminate thesemiconductor substrate 2 and the second semiconductor substrate 5 withrotating the positions of the notches or the like at an angle θ to eachother. Concretely, it is possible to use the substrates, in which theplane directions of the principal surfaces are {100} and a notches areformed in <100> directions or <110> directions of the principalsurfaces, as the semiconductor substrate 2 and the second semiconductorsubstrate 5, and laminate the semiconductor substrate 2 and the secondsemiconductor substrate 5 with rotating the portions of the notches orthe like at 45° to each other. Note that, when conducting a finealignment of the angle at the time of lamination of both wafers, amethod to laminate with aligning the position of the notch of thesemiconductor substrate 2 is advantageous.

Furthermore, the insulating film 6 is composed of an insulating materialsuch as SiN or the like and is formed by a CVD (Chemical VaporDeposition) method or the like.

Note that, after the second semiconductor substrate 5 is formed on thesemiconductor substrate 2, a bonded wafer (substrate) is obtained.

Next, as shown in FIG. 4B, for example, the cap film 13, the fin 11 andthe oxide film 4 are formed in an n-type FinFET region 10R and the capfilm 23, the fin 21 and the oxide film 4 are formed in a p-type FinFETregion 20R, respectively by patterning the insulating film 6, the secondsemiconductor substrate 5 and the oxide film 4 by photolithography andRIE (Reactive Ion Etching). Note that, since the oxide film 4 functionsas an etching stopper at this time, it is possible to preventover-etching of the semiconductor substrate 2.

At this stage, both plane directions of the side faces of the fins 11and 21 are {110} and both channel directions 11 c and 21 c are <110>.For example, when the substrate, of which the plane direction of theprincipal surface is {100} and the notch is formed in {110} direction ofthe principal surface, is used as the second semiconductor substrate 5,the fins 11 and 21 are formed to be parallel in a direction of the notchof the second semiconductor substrate 5.

Next, as shown in FIG. 4C, after forming a mask 30 on the p-type FinFETregion 20R, an impurity is selectively implanted to the n-type FinFETregion 10R and the area where the impurity has been implanted isamorphized, which results in that an amorphous region 7 is formed. Here,an impurity ion, which has relatively heavy mass enabling a Si crystalto be amorphized but does not become a conductivity type impurity, suchas Ge or the like is used for implanting. Furthermore, the impurity ionis implanted with energy and a dose amount which allow the area to besufficiently amorphized by implanting the impurity ion and preventdamage from generating at an area to be amorphized. Furthermore, theimpurity ion is preferably implanted at a predetermined angle withrespect to the surface of the semiconductor substrate 2. If implantingvertically with respect to the surface of the semiconductor substrate 2,it is necessary to implant the impurity ion to the fin 11 penetratingthrough the cap film 13 with high energy, which greatly damages thesemiconductor substrate 2 or the like.

Next, as shown in FIG. 4D, the mask 30 on the p-type FinFET region 20Ris removed.

Next, as shown in FIG. 4E, the amorphous region 7 is recrystallized byannealing treatment. Here, since the recrystallization occurs using thesemiconductor substrate 2 as a base, the crystal-axis direction of theunit cell of the crystal of the fin 11 matches that of the semiconductorsubstrate 2. Note that, the annealing treatment is conducted undermoderate conditions, for example, at 550° C. for one hour or the likesince the shape of the crystal of the fin 11 changes due to themigration of the crystal of the fin 11 if the temperature is too high orthe period of treatment is too long. Note that, as shown in FIG. 4E, itis preferable that the oxide film 4 in the n-type FinFET region 10R isdestroyed and the region where the oxide film 4 was formed isrecrystallized during the above-mentioned formation of the amorphousregion 7 and a series of processes for recrystallizing.

Next, as shown in FIG. 4F, after depositing a SiO₂ film or the like bythe CVD method or the like, the device isolation region 3 is formed byplanarizing this deposited film by CMP (Chemical Mechanical Polishing)using the upper surface of the cap films 13 and 23 as a stopper.

Next, as shown in FIG. 4G, the planarized device isolation region 3 isetched back up to a predetermined height. For example, when the heightof the fins 11 and 21 from the surface of the semiconductor substrate 2is 200 nm, the device isolation region 3 is 100 nm.

Next, as shown in FIG. 4H, a conductivity type impurity ion is implantedto the n-type FinFET region 10R by an ion implantation procedure afterforming a mask 31 on the p-type FinFET region 20R, which results in thata punch-through stopper (not shown) is formed in a region locatedsubstantially below the upper surface of the device isolation region 3of the fin 11. Here, a p-type impurity ion such as B, BF₂, In or thelike is used for the conductivity type impurity.

Concretely, a punch-through stopper is formed by following method. Aconductivity type impurity is implanted to the n-type FinFET region 10Rfrom a direction vertical to the surface of the semiconductor substrate2 and so as to be implanted to the device isolation region 3. Theconductivity type impurity implanted to the device isolation region 3 isscattered through a large angle and the conductivity type impurityscattered in a transverse direction is diffused into the fin 11, whichresults in that a punch-through stopper is formed. Note that, since theconductivity type impurity is implanted from a direction vertical to thesurface of the semiconductor substrate 2, the conductivity type impurityis hardly implanted to the fin 11 directly, and the punch-throughstopper is formed only in a region located substantially below the uppersurface of the device isolation region 3 by the conductivity typeimpurity implanted via device isolation region 3.

Next, as shown in FIG. 4I, a conductivity type impurity ion is implantedto the p-type FinFET region 20R by an ion implantation procedure afterforming a mask 32 on the n-type FinFET region 10R, which results in thata punch-through stopper (not shown) is formed in a region locatedsubstantially below the upper surface of the device isolation region 3of the fin 21. Here, an n-type impurity ion such as As, P or the like isused for the conductivity type impurity ions. A formation method of thepunch-through stopper is same as that in the fin 11.

Next, as shown in FIG. 4J, after forming the gate insulating films 12and 22 on the side faces of the fins 11 and 21, a gate electrodematerial film 8 is deposited on the semiconductor substrate 2 by the CVDmethod or the like and is planarized by the CMP using the upper surfaceof the cap films 13 and 23 as a stopper.

Concretely, the gate insulating films 12 and 22 are formed by followingmethod. For example, the gate insulating films 12 and 22 are formed byoxidation of the side face of the fins 11 and 21 in case of using a SiO₂film as the gate insulating films 12 and 22, and by nitridation oroxynitridation after oxidation of the side face of the fins 11 and 21 incase of using a SiON film. Furthermore, when using a SiN film, a high-kmaterial film or the like as the gate insulating films 12 and 22, thegate insulating films 12 and 22 may be formed by removing an unnecessaryportion after depositing the SiN film, the high-k material film or thelike on the whole surface of the semiconductor substrate 2 by the CVDmethod or the like.

Next, as shown in FIG. 4K, for example, the gate electrode material film8 is patterned by the photolithography and the RIE, and then, processedinto the gate electrodes 14 and 24. After that, regions of the cap films13, 23 and the gate insulating films 12 and 22 which are not surroundedby the gate electrodes 14 and 24 are removed by etching.

After that, although it is not shown in the figures, the conductivitytype impurity ion is implanted to the fins 11 and 21 using the gateelectrodes 14 and 24 as a mask to form extension regions of thesource/drain regions 11 a and 21 a in the fins 11 and 21, respectively.Here, an n-type impurity is implanted to the fin 11 to form an n-typeextension region. Meanwhile, a p-type impurity is implanted to the fin21 to form a p-type extension region. After that, the conductivity typeimpurity ions in the n-type and p-type extension regions are activatedby applying activation annealing.

Next, gate sidewalls are formed on the side faces of the gate electrodes14 and 24, respectively. Next, the conductivity type impurity isimplanted to the fins 11 and 21 by an ion implantation procedure or thelike using the gate electrodes 14 and 24 and the gate sidewalls on theside faces thereof as a mask, which results in that the source/drainregions 11 a and 21 a are formed in the fins 11 and 21, respectively.Here, the conductivity type impurity having the same conductivity typeas the one used for forming the extension region is used. After that,the conductivity type impurity in the source/drain regions 11 a and 21 aare activated by applying another activation annealing.

Note that, the source/drain regions 11 a and 21 a are temporarilyamorphized since they are formed by an ion implantation. As a result, ifthe heights of the fins 11 and 21 are not sufficient and thesource/drain regions 11 a and 21 a are located near the semiconductorsubstrate 2, during the heat treatment after the ion implantation, thereis a risk that the source/drain regions 11 a and 21 a are recrystallizedusing the second semiconductor substrate 5 as a base and thecrystal-axis direction of the unit cell of the fin 21 may possibly matchthat of the semiconductor substrate 2 just like the fin 11. Therefore,the fins 11 and 21 are preferably formed so as to have a sufficientheight with respect to the depth of the source/drain regions 11 a and 21a in the height direction of the fins 11 and 21.

Next, a silicide layer is formed on the upper surfaces of the gateelectrodes 14 and 24 and the surfaces of the fins 11 and 21 bydepositing a metal film on the semiconductor substrate 2 and applyingheat treatment.

According to the first embodiment, the semiconductor device 1 having then-type FinFET 10 and the p-type FinFET 20, which have an optimal channeldirection with respect to the crystal axis in order to improve thecarrier mobility and enable to be formed in a preferable layout, on thesame substrate (which is semiconductor substrate 2) can be formed.

The preferable layout is that, for example, the n-type FinFET 10 and thep-type FinFET 20 are parallel or vertical each other within the planeparallel to the surface of the semiconductor substrate 2. According tothis embodiment, since an angle formed by the n-type FinFET 10 and thep-type FinFET 20 can be freely configured by adjusting an angle tolaminate the semiconductor substrate 2 and the second semiconductorsubstrate 5 in the processes for fabricating the semiconductor device 1,it is possible to realize a preferable layout.

In a conventional technique that the plane direction of the fin sidesurfaces and the channel directions of both n-type and p-type FinFETsare configured to be a direction to improve the carrier mobility byforming n-type and p-type FinFETs disposed on a plane parallel oneanother to the surface of the semiconductor substrate 2 at apredetermined angle (for example, 45°), problems such that increase ofinstallation area or dimensional control becomes difficult andfabrication processes becomes complicated or the like occur since thelayout becomes complicated. However, according to this embodiment, suchproblems do not occur.

Note that, in general, since an electric current passing through then-type FinFET is large compared with that of the p-type FinFET, theproblem of the deterioration of gate insulating film property by a hotcarrier, threshold voltage shift or the like is likely to occur.However, when the oxide film 4 is not formed between the fin 11 of then-type FinFET 10 and the semiconductor substrate 2 and the fin 11 isconnected to the semiconductor substrate 2 with sufficient lowresistance just like this embodiment, although a hole is generated inthe fin 11 by an impact ionization phenomenon of the hot carrier, thehole can come out to the semiconductor substrate 2 side withoutremaining therein, therefore, the above-mentioned problems or asubstrate floating effect are reduced. On the other hand, since theabove-mentioned problems hardly occur in the p-type FinFET 20, there isalmost no influence to the operation reliability of the semiconductordevice 1 even if the oxide film 4 exists between the fin 21 and thesemiconductor substrate 2.

Therefore, the configuration of the semiconductor device 1 according tothis embodiment in which the oxide film 4 is not formed between the fin11 and the semiconductor substrate 2 but is formed between the fin 21and the semiconductor substrate 2 has a high operation reliability ofthe semiconductor device 1 compared with the configuration in which theoxide film 4 is not formed between the fin 21 and the semiconductorsubstrate 2 but is formed between the fin 11 and the semiconductorsubstrate 2.

Furthermore, in general, it is possible to form the semiconductor device1 having the above-mentioned effect using the cheapest substrate ofwhich the plane direction of the principal surface is {100} as thesemiconductor substrate 2 and the second semiconductor substrate 5.

Second Embodiment

The second embodiment is different from the first embodiment in that thecrystal-axis direction of the unit cell of the crystal composing the fin21 matches that of the crystal composing the semiconductor substrate 2.Note that, for the points which are same as the first embodiments, theexplanation will be omitted to simplify.

FIG. 5 is a cross sectional view of the semiconductor device accordingto the second embodiment. Note that, the cross section shown in FIG. 5corresponds to the cross section shown in FIG. 2.

For the semiconductor substrate 2, it is possible to use, for example, aSi substrate of which plane direction of the principal surface is {100}.

For the fin 21, it is preferable that the plane direction of the sideface is {110} and the channel direction 21 c of the channel region 21 bformed on the side face is <110> for the reason for improving thecarrier mobility or the like. Furthermore, the crystal-axis direction ofthe unit cell of the crystal composing the fin 21 matches that of thecrystal composing the semiconductor substrate 2.

For the fin 11, it is preferable that the plane direction of the sideface is {100} and the channel direction 11 c of the channel region 11 bformed on the side face is <100> for the reason for improving thecarrier mobility or the like. Furthermore, the oxide film 4 is formedbetween the fin 11 and the semiconductor substrate 2. The crystal-axisdirection of the unit cell of the crystal composing the fin 11 and thatof the crystal composing the semiconductor substrate 2 are mismatched ata predetermined angle θ around a direction vertical to the surface ofthe semiconductor substrate 2. This predetermined angle θ is preferablyθ=(45+90×n)° (n is an integer number).

An example of the processes for fabricating the semiconductor device 1according to this embodiment will be described hereinafter.

FIGS. 6A to 6E are cross sectional views showing processes forfabricating the semiconductor device according to the second embodiment.Note that, the cross sections shown in these figures correspond to thecross section shown in FIG. 5.

Firstly, as shown in FIG. 6A, the second semiconductor substrate 5 islaminated on the semiconductor substrate 2 and the insulating film 6 isformed thereon. Here, the second semiconductor substrate 5 is composedof, for example, a crystal substantially identical to the crystalcomposing the semiconductor substrate 2, e.g. an Si crystal.Furthermore, in the second semiconductor substrate 5, the planedirection of the principal surface is equal to that of the semiconductorsubstrate 2 and the crystal-axis direction of the unit cell is at apredetermined angle θ around a direction vertical to the surface thereofwith that of the semiconductor substrate 2. Especially, it is preferablethat the plane directions of the principal surfaces of the semiconductorsubstrate 2 and the second semiconductor substrate 5 are {100} andθ=(45+90×n)° (n is an integer number).

Following method is used for adjusting an in-plane angle of thesubstrate when laminating the semiconductor substrate 2 and the secondsemiconductor substrate 5. For example, substrates in which marksindicating directions of the crystal such as notches, orientation flatsor the like are provided in a direction preliminarily located at anangle θ to each other are used as the semiconductor substrate 2 and thesecond semiconductor substrate 5, and are laminated with aligning(matching) the positions of the notches or the like of the semiconductorsubstrate 2 and the second semiconductor substrate 5. Concretely, it ispossible to use a substrate, of which the plane direction of theprincipal surface is {100} and a notch or the like is formed in a <100>direction of the principal surface, as the semiconductor substrate 2 anda substrate, in which the {100} plane direction of the principal surfaceis {100} and a notch or the like is formed in a <110> direction of theprincipal surface, as the second semiconductor substrate 5, and laminatethe semiconductor substrate 2 and the second semiconductor substrate 5with aligning the positions of the notches or the like thereof.

Furthermore, it may use the same substrates, in which the notches or thelike are provided in the same direction, as the semiconductor substrate2 and the second semiconductor substrate 5, and laminate thesemiconductor substrate 2 and the second semiconductor substrate 5 withrotating the positions of the notches or the like at an angle θ to eachother. Concretely, it is possible to use the substrates, in which theplane directions of the principal surfaces are {100} and a notches areformed in <100> directions or <110> directions of the principalsurfaces, as the semiconductor substrate 2 and the second semiconductorsubstrate 5, and laminate the semiconductor substrate 2 and the secondsemiconductor substrate 5 with rotating the portions of the notches orthe like at 45° to each other. Note that, when conducting a finealignment of the angle at the time of lamination of both wafers, amethod to laminate with aligning the position of the notch of thesemiconductor substrate 2 is advantageous.

Next, as shown in FIG. 6B, for example, the cap film 13, the fin 11 andthe oxide film 4 are formed in the n-type FinFET region 10R and the capfilm 23, the fin 21 and the oxide film 4 are formed in the p-type FinFETregion 20R, respectively by patterning the insulating film 6, the secondsemiconductor substrate 5 and the oxide film 4 by photolithography andRIE. Note that, since the oxide film 4 functions as an etching stopperat this time, it is possible to prevent over-etching of thesemiconductor substrate 2.

At this stage, both plane directions of the side faces of the fins 11and 21 are {110} and both channel directions 11 c and 21 c are <110>.For example, when the substrate, of which the plane direction of theprincipal surface is {100} and the notch is formed in <110> direction ofthe principal surface, is used as the second semiconductor substrate 5,the fins 11 and 21 are formed to be parallel in a direction of the notchof the second semiconductor substrate 5.

Next, as shown in FIG. 6C, after forming the mask 30 on the n-typeFinFET region 10R, an impurity is selectively implanted to the p-typeFinFET region 20R and the area where the impurity has been implanted isamorphized, which results in that an amorphous region 9 is formed.

Next, as shown in FIG. 6D, the mask 30 on the n-type FinFET region 10Ris removed.

Next, as shown in FIG. 6E, the amorphous region 9 is recrystallized byannealing treatment. Here, since the recrystallization occurs using thesemiconductor substrate 2 as a base, the crystal-axis direction of theunit cell of the crystal of the fin 21 matches that of the semiconductorsubstrate 2. Note that, as shown in FIG. 6E, it is preferable that theoxide film 4 in the p-type FinFET region 20R is destroyed and the regionwhere the oxide film 4 was formed is recrystallized during theabove-mentioned formation of the amorphous region 9 and a series ofprocesses for recrystallizing.

After that, a process following the formation process of the deviceisolation region 3 shown in FIG. 4F is carried out in a same way as thefirst embodiment.

According to the second embodiment, it is possible to obtain an effectsimilar to the first embodiment by the semiconductor device 1 having aconfiguration different from the first embodiment. Note that, sinceoxide film 4 is formed between the fin 11 and the semiconductorsubstrate 2, the electron hole generated in the fin 11 by the impactionization phenomenon of the hot carrier cannot come out to thesemiconductor substrate 2 side and the operation reliability of thesemiconductor device 1 is possibly inferior to that of the firstembodiment, however, it is acceptable as long as this problem due to theimpact ionization phenomenon of the hot carrier is an application at alevel that the operation reliability of the semiconductor device 1 isnot really affected.

Third Embodiment

The third embodiment is different from the first embodiment in a part ofthe method for fabricating the semiconductor device 1. Note that, forthe points which are same as the first embodiments, the explanation willbe omitted to simplify.

An example of the processes for fabricating a semiconductor device 1according to this embodiment will be described hereinafter.

FIGS. 7A to 7C are cross sectional views showing processes forfabricating the semiconductor device according to the third embodiment.Note that, the cross sections shown in these figures correspond to thecross section shown in FIG. 2.

Firstly, as shown in FIG. 7A, the processes forming the cap film 13, thefin 11 and the oxide film 4 in the n-type FinFET 10, and the processesforming the cap film 23, the fin 21 and the oxide film 4 in the p-typeFinFET 20 are carried out in the same way as the first embodiment.

Next, as shown in FIG. 7B, after depositing a SiO₂ film or the like bythe CVD method or the like, the device isolation region 3 is formed byplanarizing this deposited film by the CMP using the upper surface ofthe cap films 13 and 23 as a stopper.

Next, as shown in FIG. 7C, after forming a mask 33 on the p-type FinFETregion 20R, an impurity is selectively implanted to the n-type FinFETregion 10R and the area where the impurity has been implanted isamorphized via the device isolation region 3 of the semiconductorsubstrate 2, which results in that an amorphous region 7 is formed.

Following this, by removing the mask 33 on the p-type FinFET region 20Rand recrystallizing the amorphous region 7 by the annealing treatment,the status becomes same as shown in FIG. 4F. Here, since therecrystallization occurs using the semiconductor substrate 2 as a base,the crystal-axis direction of the unit cell of the crystal of the fin 11matches that of the semiconductor substrate 2.

After this, the process following the etch back process of the deviceisolation region 3 shown in FIG. 4G is carried out in the same way asthe first embodiment.

According to the third embodiment, since the side face of the fin 11 iscovered by the device isolation region 3, although the fin 11 is thinand has a risk to be damaged or destroyed as being unsustainable againstthe damage by the impurity implantation for forming the amorphous region7, it is possible to hold the fin 11 by the device isolation region 3when forming the amorphous region 7. Note that, since the damage isrepaired by recrystallizing, there is no risk of the damage ordestruction after the recrystallization.

Obviously, this embodiment can be combined with the second embodiment,and in this case, the device isolation region 3 is to be a support ofthe fin 21 when amorphizing the fin 21.

Fourth Embodiment

The fourth embodiment is different from the first embodiment in thatstrain generating films 15 and 25 for generating a strain in the channelregions 11 b and 21 b of the n-type FinFET 10 and the p-type FinFET 20are formed. Note that, for the points which are same as the firstembodiments, the explanation will be omitted to simplify.

FIG. 8 is a cross sectional view of the semiconductor device accordingto the fourth embodiment. Note that, the cross section shown in FIG. 8corresponds to the cross section of the semiconductor device 1 of thefirst embodiment shown in FIG. 2.

The strain generating film 15 is formed so as to cover the whole n-typeFinFET 10 and has a function to improve the mobility of the electron bygenerating a strain in the channel region 11 b in the fin 11. Thestrains generated in the channel region 11 b by the strain generatingfilm 15 are specifically a tensile strain in the channel direction, acompressive strain in a height direction of the fin 11 and a compressivestrain in a thickness direction of the fin 11.

These strain properties (compressive or tensile) match the property ofthe strain to improve the mobility of the electron of the channel region11 b in any directions when the plane direction of the side face of thefin 11 is {100} and the channel direction is a <100> direction in the{100} plane.

The strain generating film 25 is formed so as to cover the whole p-typeFinFET 20 and has a function to improve the mobility of the electronhole by generating a strain in the channel region 21 b in the fin 21.

The strain generating film 25 has a property to generate a strain, whichhas the opposite property to that of the strain generating film 15, inan object and the strains generated in the channel region 21 b by thestrain generating film 25 are specifically a compressive strain in thechannel direction, a tensile strain in a height direction of the fin 21and a tensile strain in a thickness direction of the fin 21.

These strain properties (compressive or tensile) match the property ofthe strain to improve the mobility of the electron hole of the channelregion 21 b in any directions when the plane direction of the side faceof the fin 21 is {110} and the channel direction is a <110> direction inthe {110} plane.

Namely, it is preferable to form the fin 11 so that the plane directionof the side face is {100} and the channel direction is a <100> directionin the {100} plane, and to form the fin 21 so that the plane directionof the side face is {110} and the channel direction is a <110> directionin the {110} plane from the viewpoint of improvement of the carriermobility by the strain generating films 15 and 25.

Note that, for example, when the fin 11 is formed so that the planedirection of the side face is {110} and the channel direction is a <100>direction in the {110} plane just like the fin 21, the properties of thestrain to improve the mobility of the electron are a tensile strain inthe channel direction, a compressive strain in a height direction of thefin 11 and a tensile strain in a thickness direction of the fin 11, andthe strain in the thickness direction of the fin 11 does not match theproperty of the strain actually generated. As a result, there is a riskthat the mobility of the electron is reduced compared with theabove-mentioned preferable case.

For the strain generating films 15 and 25, it is possible to use a SiNfilm formed by the CVD method or the like. In this case, it is possibleto form the strain generating films 15 and 25 separately by adjustingthe level of the strain generating in the object and the properties(compressive or tensile) by controlling hydrogen concentration in theSiN film.

Furthermore, the strain generating films 15 and 25 can be used as anetching stopper when etching an interlayer insulating film (not shown)formed on the strain generating films 15 and 25 to form a contact plug(not shown) or the like.

According to the fourth embodiment, it is possible to improve thecarrier mobility of the channel regions 11 c and 21 c and, as a result,improve current characteristics of the n-type FinFET 10 and the p-typeFinFET 20 by forming the strain generating films 15 and 25.

Furthermore, as shown in the first embodiment, since it is possible toform the fins 11 and 21 varying the channel direction with respect tothe crystal axis, it is possible to match the property of the straingenerated from the strain generating films 15 and 25 with the propertyof the strain to improve the carrier mobility in the fins 11 and 21. Asa result, it is possible to obtain the effect to improve the carriermobility more effectively for both of the n-type FinFET 10 and thep-type FinFET 20.

Furthermore, as shown in the first embodiment, since the fins 11 and 21can be formed parallel or vertical to each other, it is possible to formthe strain generating films 15 and 25 relatively easily. For example,when the fins 11 and 21 are formed within the plane parallel to thesurface of the semiconductor substrate 2 at an angle of 45° one another,the layout of the strain generating films 15 and 25 becomes complicated,which occurs the problems such that the formation of the straingenerating films 15 and 25 becomes difficult or the like.

Other Embodiments

It should be noted that embodiments are not intended to be limited tothe above-mentioned first to fourth embodiments, and the various kindsof changes thereof can be implemented by those skilled in the artwithout departing from the gist of the invention. For example, it ispossible to lower electric resistivity by epitaxially growing a crystalsuch as Si or the like on the surface of the fins 11 and 21 to increasethe thickness of the fins 11 and 21. Note that, when epitaxially growinga crystal having a lattice constant different from that of Si such as aSiGe crystal, a SiC crystal or the like, it is possible to improve thecarrier mobility by generating an appropriate strain in the channelregions 11 b and 21 b of the fins 11 and 21.

Furthermore, in the above-mentioned first to fourth embodiments,although it is explained that the plane directions of the principalsurface of the semiconductor substrate 2 and the second semiconductorsubstrate 5 are {100}, the plane direction of the principal surfacethereof is not limited thereto, for example, it may be {110}.

Furthermore, it is possible to arbitrarily combine the configurations ofthe above-mentioned first to fourth embodiments without departing fromthe gist of the invention.

Furthermore, the embodiments include the semiconductor device havingfollowing structure.

A semiconductor device comprising a semiconductor substrate, a firsttransistor formed on the semiconductor substrate comprising a crystal ofwhich axial angle is substantially identical to that of thesemiconductor substrate, which has a first fin of which crystal-axisdirection of the unit cell substantially matches that of thesemiconductor substrate, and a second transistor formed on thesemiconductor substrate comprising a crystal of which axial angle issubstantially identical to that of the semiconductor substrate, whichhas a second fin in which the crystal-axis direction of the unit cellthereof is at a predetermined angle around a direction vertical to thesurface of the semiconductor substrate with that of the semiconductorsubstrate.

A semiconductor device comprising a semiconductor substrate in which oneof crystal axes of the unit cell faces to a direction vertical to thesurface of the semiconductor substrate and two of them face to adirection along the plane parallel to the surface of the semiconductorsubstrate, a first transistor formed on the semiconductor substratecomprising a crystal of which axial angle is substantially identical tothat of the semiconductor substrate, which has a first fin of whichcrystal-axis direction of the unit cell is substantially identical tothat of the semiconductor substrate, and a second transistor formed onthe semiconductor substrate comprising a crystal of which axial angle issubstantially identical to that of the semiconductor substrate, whichhas a second fin in which one of crystal axes faces to a directionvertical to the surface of the semiconductor substrate and two of themface to a direction different from the crystal-axis direction of theunit cell of the semiconductor substrate along the plane parallel to thesurface of the semiconductor substrate.

1-9. (canceled)
 10. A method of fabricating a semiconductor device,comprising: laminating a second substrate, of which plane direction ofthe principal surface is same as that of a first substrate, on the firstsubstrate in the state that the crystal-axis directions in the principalsurfaces of the first and second substrates are at a predetermined anglearound a direction vertical to the principal surface to each other,forming first and second fins by patterning the second substrate,selectively amorphizing the first fin; and substantially matching thecrystal-axis direction of the unit cell of the first fin to that of thefirst substrate by recrystallizing the amorphized first fin using thefirst substrate as a base.
 11. The method of fabricating a semiconductordevice according to claim 10, wherein the plane directions of theprincipal surface of the first and second substrates are {100}; and thepredetermined angle is (45+90×n)° (n is an integer number).
 12. Themethod of fabricating a semiconductor device according to claim 10,wherein the first and second substrates are laminated by forminghydrophilic bonding or hydrophobic bonding between the first and secondsubstrates.
 13. The method of fabricating a semiconductor deviceaccording to claim 10, wherein the first and second substrates havenotches or an orientation flats provided in the crystal-axis directionsat a predetermined angle to each other; and the first substrate and thesecond substrate are laminated by aligning the positions of therespective notches or orientation flats.
 14. The method of fabricating asemiconductor device according to claim 10, wherein the first and secondsubstrates have notches or orientation flats provided in the samecrystal-axis direction; and the first substrate and the second substrateare laminated with rotating a position of the respective notches ororientation flats at a predetermined angle to each other.
 15. The methodof fabricating a semiconductor device according to claim 10, wherein thefirst fin is selectively amorphized by implanting impurity ions which donot function as a conductivity type impurity.
 16. The method offabricating a semiconductor device according to claim 10, whereinsource/drain regions of different conductivity types are formed on thefirst and second fins after recrystallizing the first fin.
 17. Themethod of fabricating a semiconductor device according to claim 10,wherein an oxide film is formed on an interface of the first and secondsubstrates when laminating the first and second substrates; and theoxide film between the first fin and the first substrate is destroyedand a region in which the oxide film has been destroyed isrecrystallized by amorphizing and recrystallizing the first fin.
 18. Themethod of fabricating a semiconductor device according to claim 10,wherein n-type and p-type source/drain regions are formed in the firstand second fins, respectively after recrystallizing the first fin. 19.The method of fabricating a semiconductor device according to claim 10,wherein the first fin is amorphized after forming a device isolationregion so as to cover side faces of the first and second fins.
 20. Themethod of fabricating a semiconductor device according to claim 10,wherein gate electrodes are formed via gate insulating films so as tosandwich both side faces of the first and second fins, respectivelyafter recrystallizing the first fin, then, first and second transistorsare formed; and first and second strain generating films for generatinga strain in channel regions of the first and second transistors,respectively, are formed on the first and second transistors.